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integrated circuit systems, inc. ICS95V857C 1190a?12/16/05 block diagram 2.5v wide range frequency clock driver (45mhz - 233mhz) pin configuration 48-pin tssop/tvsop recommended application: ddr memory modules / zero delay board fan out provides complete ddr registered dimm solution with icssstvf16857, icssstvf16859 or icssstv32852 product description/features: low skew, low jitter pll clock driver 1 to 10 differential clock distribution (sstl_2) feedback pins for input to output synchronization pd# for power management spread spectrum-tolerant inputs auto pd when input signal removed specifications: meets pc3200 class a+ specification for ddr-i 400 support covers all ddri speed grades switching characteristics: cycle - cycle jitter: <50ps output - output skew: <40ps period jitter: 30ps s t u p n is t u p t u o e t a t s l l p d d v a# d pt n i _ k l cc n i _ k l ct k l cc k l ct t u o _ b fc t u o _ b f d n gh l h lh l h f f o / d e s s a p y b d n gh h l hl h l f f o / d e s s a p y b v 5 . 2 ) m o n ( ll hzzz z f f o v 5 . 2 ) m o n ( lh lzzz z f f o v 5 . 2 ) m o n ( hl hlhl h n o v 5 . 2 ) m o n ( hh l hlh l n o v 5 . 2 ) m o n ( x) z h m 0 2 < ) 1 ( zz z z f f o functionality pll fb_int fb_inc clk_inc clk_int pd# control logic fb_outt fb_outc clkt0 clkt1 clkt2 clkt3 clkt4 clkt5 clkt6 clkt7 clkt8 clkt9 clkc0 clkc1 clkc2 clkc3 clkc4 clkc5 clkc6 clkc7 clkc8 clkc9 6.10 mm body, 0.50 mm pitch = tssop 4.40 mm body, 0.40 mm pitch = tvsop gnd clkc0 clkt0 vdd clkt1 clkc1 gnd gnd clkc2 clkt2 vdd vdd clk_int clk_inc vdd avdd agnd gnd clkc3 clkt3 vdd clkt4 clkc4 gnd gnd clkc5 clkt5 vdd clkt6 clkc6 gnd gnd clkc7 clkt7 vdd pd# fb_int fb_inc vdd fb_outc fb_outt gnd clkc8 clkt8 vdd clkt 9 clkc 9 gnd ics 9 5v857c 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 9 20 21 22 23 24 48 47 46 45 44 43 42 41 40 3 9 38 37 36 35 34 33 32 31 30 2 9 28 27 26 25
2 ICS95V857C 1190a?12/16/05 pin configuration 40-pin mlf 56-ball bga top view gnd clkc2 clkt2 vdd clk_int clk_inc vdd avdd agnd gnd clkc7 clkt7 vdd pd# fb_int fb_inc vdd vdd fb_outc fb_outt clkc3 clkt3 vdd clkt4 clkc4 clkc 9 clkt 9 vdd clkt8 clkc8 clkc1 clkt1 vdd clkt0 clkc0 clkc5 clkt5 vdd clkt6 clkc6 1 10 11 20 21 31 30 40 ics95v 8 57c a b 123456 c d e f g h j k 12345 6 a clkt0 clkc0 gnd gnd clkc5 clkt5 b clkc1 clkt1 vdd vdd clkt6 clkc6 c gnd gnd nc nc gnd gnd d clkt2 clkc2 nc nc clkc7 clkt7 e vdd vdd nb nb vdd pd# f clk_int clk_inc nb nb fb_inc fb_int g vdd avdd nc nc fb_outc vdd h agnd gnd nc nc gnd fb_outt j clkc3 clkt3 vdd vdd clkt8 clkc8 k clkt4 clkc4 gnd gnd clkc9 clkt9
3 ICS95V857C 1190a?12/16/05 pin descriptions e m a n n i pe p y tn o i t p i r c s e d d d vr w pv 5 . 2 , y l p p u s r e w o p d n gr w pd n u o r g d d v ar w pv 5 . 2 , y l p p u s r e w o p g o l a n a d n g ar w pd n u o r g g o l a n a ) 0 : 9 ( t k l ct u os t u p t u o r i a p l a i t n e r e f f i d f o k c o l c " e u r t " ) 0 : 9 ( c k l ct u os t u p t u o r i a p l a i t n e r e f f i d f o s k c o l c " y r a t n e m e l p m o c " c n i _ k l cn it u p n i k c o l c e c n e r e f e r " y r a t n e m e l p m o c " t n i _ k l cn it u p n i k c o l c e c n e r e f e r " e u r t " c t u o _ b ft u o t i . k c a b d e e f l a n r e t x e r o f d e t a c i d e d , t u p t u o k c a b d e e f " y r a t n e m e l p m o c " d e r i w e b t s u m t u p t u o s i h t . k l c e h t s a y c n e u q e r f e m a s e h t t a s e h c t i w s c n i _ b f o t t t u o _ b ft u o s e h c t i w s t i . k c a b d e e f l a n r e t x e r o f d e t a c i d e d , t u p t u o k c a b d e e f " " e u r t " o t d e r i w e b t s u m t u p t u o s i h t . k l c e h t s a y c n e u q e r f e m a s e h t t a t n i _ b f t n i _ b fn i r o f l l p l a n r e t n i e h t o t l a n g i s k c a b d e e f s e d i v o r p , t u p n i k c a b d e e f " e u r t " r o r r e e s a h p e t a n i m i l e o t t n i _ k l c h t i w n o i t a z i n o r h c n y s c n i _ b fn i l l p l a n r e t n i e h t o t l a n g i s s e d i v o r p , t u p n i k c a b d e e f " y r a t n e m e l p m o c " r o r r e e s a h p e t a n i m i l e o t c n i _ k l c h t i w n o i t a z i n o r h c n y s r o f # d pn it u p n i s o m c v l . n w o d r e w o p this pll clock buffer is designed for a v dd of 2.5v, an av dd of 2.5v and differential data input and output levels. the ICS95V857C is a zero delay buffer that distributes a differential clock input pair (clk_inc, clk_int) to ten differential pair of clock outputs (clkt[0:9], clkc[0:9]) and one differential pair feedback clock output (fb_out, fb_outc). the clock outputs are controlled by the input clocks (clk_inc, clk_int), the feedback clocks (fb_int, fb_inc), the 2.5-v lvcmos input (pd#) and the analog power input (av dd ). when input (pd#) is low while power is applied, the receivers are disabled, the pll is turned off and the differential clock outputs are tri-stated. when av dd is grounded, the pll is turned off and bypassed for test purposes. when the input frequency is less than the operating frequency of the pll, appproximately 20mhz, the device will enter a low power mode. an input frequency detection circuit on the differential inputs, independent from the input buffers, will detect the low frequency condition and perform the same low power features as when the (pd#) input is low. when the input frequency increases to greater than approximately 20 mhz, the pll will be turned back on, the inputs and outputs will be enabled and pll will obtain phase lock between the feedback clock pair (fb_int, fb_inc) and the input clock pair (clk_inc, clk_int). the pll to the ICS95V857C clock driver uses the input clocks (clk_inc, clk_int) and the feedback clocks (fb_int, fb_inc) provide high-performance, low-skew, low-jitter, output differential clocks (clkt[0:9], clkc[0:9]). the ICS95V857C is also able to track spread spectrum clock (ssc) for reduced emi. the ICS95V857C is characterized for operation from 0c to 85c, and will meet jedec standard 82-1 and 82-1a class a+ for registered ddr clock drivers.
4 ICS95V857C 1190a?12/16/05 absolute maximum ratings supply voltage (vdd & avdd). . . . . . . . . . . -0.5v to 4.6v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd + 0.5 v ambient operating temperature . . . . . . . . . . 0c to +85c storage temperature . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 85c; supply voltage a vdd , v dd = 2.5v 0.2v parameter symbol conditions min typ max units input high current i ih v i = v dd or gnd 5 a input low current i il v i = v dd or gnd 5 a i dd2. 5 c l = 0pf @ 200mhz 148 170 ma i ddpd c l = 0pf 100 a output high current i oh v dd = 2.3v, v out = 1v -18 -32 ma output low current i ol v dd = 2.3v, v out = 1.2v 26 35 ma high impedance out p ut current i oz v dd =2.7v, vout=v dd or gnd 10 ma input clamp voltage v ik v ddq = 2.3v iin = -18ma -1.2 v v dd = min to max, i oh = -1 ma v ddq - 0.1 v v ddq = 2.3v, i oh = -12 ma 1.7 v v dd = min to max i ol =1 ma 0.1 v v ddq = 2.3v i oh =12 ma 0.6 v input capacitance 1 c in v i = gnd or v dd 3pf output capacitance 1 c out v out = gnd or v dd 3pf 1 guaranteed by design at 220mhz, not 100% tested in production. operating supply current high-level output voltage v oh low-level output voltage v ol
5 ICS95V857C 1190a?12/16/05 recommended operating condition ( see note1 ) t a = 0 - 85c; supply voltage avdd, vdd = 2.5 v +/- 0.2v (unless otherwise stated) parameter symbol conditions min typ max units supply voltage v dd , a vdd 2.3 2.5 2.7 v clkt, clkc, fb_inc 0.4 v dd /2 - 0.18 v pd# -0.3 0.7 v clkt, clkc, fb_inc v dd /2 + 0.18 2.1 v pd# 1.7 v dd + 0.6 v dc input signal voltage (note 2) v in -0.3 v dd + 0.3 v dc - clkt, fb_int 0.36 v dd + 0.6 v ac - clkt, fb_int 0.7 v dd + 0.6 v output differential cross - voltage (note 4) v ox v dd /2 - 0.15 v dd /2 + 0.15 v input differential cross- voltage (note 4) v ix v dd /2 - 0.2 v dd /2 v dd /2 + 0.2 v high level output current i oh -6.4 ma low level output current i ol 5.5 ma operating free-air temperature t a 085c differential input signal voltage (note 3) v id low level input voltage v il high level input voltage v ih notes: 1. unused inputs must be held high or low to prevent them from floating. 2. dc input signal voltage specifies the allowable dc execution of differential input. 3. differential inputs signal voltages specifies the differential voltage [vtr-vcp] required for switching, where vt is the true input level and vcp is the complementary input level. 4. differential cross-point voltage is expected to track variations of v dd and is the voltage at which the differential signal must be crossing.
6 ICS95V857C 1190a?12/16/05 notes: 1. refers to transition on noninverting output in pll bypass mode. 2. while the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. this is due to the formula: duty cycle=t wh /t c , where the cycle (t c ) decreases as the frequency goes up. 3. switching characteristics guaranteed for application frequency range. 4. static phase offset shifted by design. timing requirements t a = 0 - 85c; supply voltage a vdd , v dd = 2.5 v +/- 0.2v (unless otherwise stated) parameter symbol conditions min max units max clock frequency freq op 2.5v+ 0.2v @ 25 o c 45 233 mhz application frequency range freq app 2.5v+ 0.2v @ 25 o c 95 220 mhz input clock duty cycle d tin 40 60 % clk stabilization t stab 15 s switching characteristics (see note 3) parameter symbol condition min typ max units low-to high level propagation delay time t plh 1 clk_in to any output 3.5 ns high-to low level propagation delay time t pll 1 clk_in to any output 3.5 ns output enable time t en pd# to any output 3 ns output disable time tdis pd# to any output 3 ns period jitter t j it (p er ) 100mhz to 200mhz -30 30 ps half-period jitter t(jit_hper) 100mhz to 200mhz -75 75 ps input clock slew rate t sl ( i ) 14v/ns output clock slew rate t sl ( o ) 12v/ns cycle to cycle jitter 1 t c y c -t c y c 100mhz to 200mhz -50 50 ps static phase offset t ( static p hase offset ) 4 -50 0 50 ps output to output skew t skew 40 ps
7 ICS95V857C 1190a?12/16/05 gnd ics 9 5v857 v dd v dd /2 v (clkc) v (clkc) scope c=14p f -v dd/2 -v dd/2 -v dd/2 v dd/2 z=60 ? z=60 ? z=50 ? z=50 ? r=10 ? r=10 ? r=50 ? r=60 ? r=60 ? r=50 ? v (tt) v (tt) c=14pf note: v (tt) = gnd t c(n) t c(n+1) t jit(cc) =t c(n) t c(n+1) figure 1. ibis model output load figure 2. output load test circuit y , fb_outc x y , fb_outt x parameter measurement information ics 9 5v857 figure 3. cycle-to-cycle jitter
8 ICS95V857C 1190a?12/16/05 (n is a large number of samples) t ( ) n+1 t ()n t () = 1 n= n t ()n n clk_inc clk_int fb_inc fb_int t (sk_o) y # x y , fb_outc x y , fb_outt x y , fb_outc x y , fb_outt x y , fb_outc x y , fb_outt x y x parameter measurement information figure 4. static phase offset figure 5. output skew 1 f o t = t - (jit_per) c(n) 1 f o figure 6. period jitter
9 ICS95V857C 1190a?12/16/05 clock inputs and outputs 80% 20% 80% 20% rise t sl fall t sl v id ,v od figure 8 . input and output slew rates parameter measurement information t (hper_n) t (hper_n+1) 1 f o y , fb_outc x y , fb_outt x figure 7. half-period jitter t =- (jit_hper) t (jit_hper_n) 1 2xf o
10 ICS95V857C 1190a?12/16/05 ordering information index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c 6.10 mm. body, 0.50 mm. pitch tssop (240 mil) (0.020 mil) min max min max a--1.20--.047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b0.170.27.007.011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l0.450.75.018.030 n a0808 aaa -- 0.10 -- .004 variations min max min max 48 12.40 12.60 .488 .496 10-0039 n d mm. d (inch) r ef erence do c.: jedec pub li cat io n 9 5, m o- 153 0.50 basic 0.020 basic see variations see variations see variations see variations 8.10 basic 0.319 basic symbol in millimeters in inches common dimensions common dimensions example: ICS95V857Cglf-t designation for tape and reel packaging lead free, rohs compliant (optional) package type g = tssop revision designator (will not correlate with datasheet revision) device type prefix ics = standard device ics xxxx y g (lf) - t
11 ICS95V857C 1190a?12/16/05 index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c ordering information min max min max a-- 1.20 --.047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.13 0.23 .005 .009 c 0.09 0.20 .0035 .008 d e e1 4.30 4.50 .169 .177 e l 0.45 0.75 .018 .030 n a0 8 0 8 aaa -- 0.08 -- .003 variations min max min max 48 9.60 9.80 .378 .386 10-0037 n d mm. d (inch) reference do c.: jedec p ublicatio n 95, m o-153 0.40 basic 0.016 basic see variations see variations see variations see variations 6.40 basic 0.252 basic symbol in millimeters in inches common dimensions common dimensions 4.40 mm. body, 0.40 mm. pitch tssop (173 mil) (16 mil) example: ICS95V857Cllf-t designation for tape and reel packaging lead free, rohs compliant (optional) package type l = tssop (tvsop) revision designator (will not correlate with datasheet revision) device type prefix ics = standard device ics xxxx y k (lf)- t
12 ICS95V857C 1190a?12/16/05 example: ICS95V857Cklf-t ordering information designation for tape and reel packaging lead free, rohs compliant (optional) package type k = mlf revision designator (will not correlate with datasheet revision) device type prefix ics = standard device ics xxxx y k (lf) - t to p vi e w index area 1 e d sawn singulation anvil singulation o r a 0.08 c c a3 a1 seating p lane e2 e2 2 l (n -1)x e (ref.) d (ref.) n&n even d e n e d2 2 d2 d e (ref.) n&n odd 1 2 e 2 (typ.) if n & n are even (n -1)x e (ref.) e e d b thermal base 2 n all dimensions in millimeters n symbol min. max. n d a0.801.00 n e a1 0 0.05 d x e basic a3 d2 min. / max. b 0.18 0.30 e2 min. / max. e l min. / max. 10-0053 source reference: mlf2? s e thermally enhanced, very thin, fine pitch quad flat / no lead plastic package 0.30 / 0.50 0.25 reference 0.50 basic 6.00 x 6.00 2.75 / 3.05 2.75 / 3.05 40 10 10
13 ICS95V857C 1190a?12/16/05 ordering information example: ICS95V857Chlf-t - e - typ b ref b ref alpha designations for vertical grid (letters i, o, q & s not used) alpha designations for vertical grid (letters i, o, q & s not used) numeric designations for horizontal grid numeric designations for horizontal grid h typ h typ c ref c ref a b c d top view a1 3 2 1 4 seating plane seating plane c t 0.12 c d typ e d d1 d1 d1 d1 d1 - e - - e - - e - e1 typ typ d e t e horiz vert total d h d1 e1 b c min/max min/max min/max 7.00 bsc 4.50 bsc 0.86/1.00 0.65 bsc 6 10 60 0.35/0.45 0.15/0.21 5.85 bsc 3.25 bsc 0.575 0.625 ** * source ref.: jedec publication 95, 10-0055 all dimensions in millimeters ref. dimensions ----- ball grid ----- max. note: ball g rid total indicates maximum ball count for p acka g e. lesser q uantit y ma y be used. mo-205*, mo-225** designation for tape and reel packaging lead free, rohs compliant (optional) package type h = bga revision designator (will not correlate with datasheet revision) device type prefix ics = standard device ics xxxx y h (lf) - t

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